Espressif Systems /ESP32-C2 /SPI1 /SUS_STATUS

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Interpret as SUS_STATUS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FLASH_SUS)FLASH_SUS 0 (WAIT_PESR_CMD_2B)WAIT_PESR_CMD_2B 0 (FLASH_HPM_DLY_128)FLASH_HPM_DLY_128 0 (FLASH_RES_DLY_128)FLASH_RES_DLY_128 0 (FLASH_DP_DLY_128)FLASH_DP_DLY_128 0 (FLASH_PER_DLY_128)FLASH_PER_DLY_128 0 (FLASH_PES_DLY_128)FLASH_PES_DLY_128 0 (SPI0_LOCK_EN)SPI0_LOCK_EN

Description

SPI1 flash suspend status register

Fields

FLASH_SUS

The status of flash suspend, only used in SPI1.

WAIT_PESR_CMD_2B

1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.

FLASH_HPM_DLY_128

1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.

FLASH_RES_DLY_128

1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.

FLASH_DP_DLY_128

1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.

FLASH_PER_DLY_128

Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.

FLASH_PES_DLY_128

Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.

SPI0_LOCK_EN

1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.

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